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preliminary datasheet R1EV24002ASAS0I two-wire serial interface 2k eeprom (256-word ? 8-bit) r10ds0122ej0100 rev.1.00 a ug. 23, 2012 description r1ev24xxx series are two-wire serial interface eeprom (e lectrically erasable and pr ogrammable rom). they realize high speed, low power consumption and a high level of reliability by employing advanced monos memory technology and cmos process. features ? single supply: 2.5 v to 5.5 v ? two-wire serial interface (i 2 c serial bus) ? clock frequency: 400 khz ? power dissipation: ? standby: 2 ? a (max) ? active (read): 1 ma (max) ? active (write): 2.5 ma (max) ? automatic page write: 8-byte/page ? write cycle time: 5 ms ? endurance: 1,000k cycles @25 ? c ? data retention: 100 years @25 ? c ? small size packag es: sop-8pin ? shipping tape and reel ? sop 8-pin: 4,000 ic/reel ? temperature range: ? 40 to +85 ? c ? lead free products. ? halogen free products. preliminary: the specifications of this device are subject to change without notice. please contact your nearest renesas electronics? sales dept. regarding specifications. r10ds0122ej0100 rev.1.00 page 1 of 15 aug. 23, 2012
R1EV24002ASAS0I preliminary ordering information orderable part numbers internal organization package shipping tape and reel R1EV24002ASAS0I#k0 2k bit (256 ? 8-bit) 150 mil 8-pin plastic sop prsp0008df-b (fp-8dbv) lead free, halogen free 4,000 ic/reel pin arrangement 1 2 3 4 8 7 6 5 a0 a1 a2 v ss v cc wp scl sd a (top view) 8-pin sop pin description pin name function a0 to a2 device address scl serial clock input sda serial data input/output wp write protect v cc power supply v ss ground block diagram control logic high voltage generator address generator x decoder y decoder memory array y-select & sense amp. serial-parallel converter v cc v ss wp scl sda a 0, a1, a2 r10ds0122ej0100 rev.1.00 page 2 of 15 aug. 23, 2012
R1EV24002ASAS0I preliminary r10ds0122ej0100 rev.1.00 page 3 of 15 aug. 23, 2012 absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ? 0.6 to +7.0 v input voltage relative to v ss vin ? 0.5 * 2 to +7.0 v operating temperature range * 1 topr ? 40 to +85 ?c storage temperature range tstg ? 55 to +125 ?c notes: 1. including electrical c haracteristics and data retention. 2. vin (min): ? 3.0 v for pulse width ? 50 ns. dc operating conditions parameter symbol min typ max unit supply voltage v cc 2.5 ?? 5.5 v v ss 0 0 0 v input high voltage v ih v cc ? 0.7 ? v cc + 0.5 v input low voltage v il ? 0.3 * 1 ? v cc ? 0.3 v operating temperature topr ? 40 ? +85 ?c note: 1. v il (min): ? 1.0 v for pulse width ? 50 ns. dc characteristics (ta = ? 40 to +85 ? c, v cc = 2.5 v to 5.5 v) parameter symbol min typ max unit test conditions input leakage current i li ? ? 2.0 ? a v cc = 5.5 v, vin = 0 to 5.5 v output leakage current i lo ? ? 2.0 ? a v cc = 5.5 v, vout = 0 to 5.5 v standby v cc current i sb ? ? 2.0 ? a v cc = 5.5 v, vin = v ss or v cc ?? 0.5 ? ? a? v cc = 3.3 v, vin = v ss or v cc , ta=25 ?c read v cc current i cc1 ? ? 1.0 ma v cc = 5.5 v, read at 400 khz ?? 0.2 ?? ma v cc = 3.3 v, read at 400 khz, ta=25 ?c write v cc current i cc2 ? ? 2.5 ma v cc = 5.5 v, write at 400 khz ?? 1.0 ?? ma v cc = 3.3 v, write at 400 khz, ta=25 ?c output low voltage v ol ? ? 0.4 v i ol = 3.0 ma capacitance (ta = +25 ? c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance (a0 to a2, scl, wp) cin * 1 ? ? 6.0 pf vin = 0 v output capacitance (sda) c i/o * 1 ? ? 6.0 pf vout = 0 v note: 1. not 100 ? tested. memory cell characteristics (v cc = 2.5 v to 5.5 v) ta=25 ?c ta=85 ?c notes endurance 1,000k cycles min. 100k cycles min 1 data retention 100 years min. 10 years min. 1 note: 1. not 100 ? tested. data of shipped sample all bits of eeprom are logical ?1? (ff hex) at shipment.
R1EV24002ASAS0I preliminary r10ds0122ej0100 rev.1.00 page 4 of 15 aug. 23, 2012 ac characteristics test conditions ? input pules levels: ? v il = 0.2 ? ? v ih = 0.8 ? ? input rise and fall time: ? ? input and output timing reference levels: 0.5 ? ? output load: ttl gate + 100 pf (ta = ? ? parameter symbol min typ max unit notes clock frequency f scl ? ? 400 khz clock pulse width low t low 1200 ? ? ns clock pulse width high t high 600 ? ? ns noise suppression time t i ? ? 50 ns 1 access time t aa 100 ? 900 ns bus free time for next mode t buf 1200 ? ? ns start hold time t hd.sta 600 ? ? ns start setup time t su.sta 600 ? ? ns data in hold time t hd.dat 0 ? ? ns data in setup time t su.dat 100 ? ? ns input rise time t r ? ? 300 ns 1 input fall time t f ? ? 300 ns 1 stop setup time t su.sto 600 ? ? ns data out hold time t dh 50 ? ? ns write protect hold time t hd.wp 1200 ? ? ns write protect setup time t su.wp 0 ? ? ns write cycle time t wc ? ? 5 ms 2 notes: 1. not 100 ? tested. 2. t wc is the time from a stop condition to the end of internally controlled write cycle.
R1EV24002ASAS0I preliminary timing waveforms bus timing t f 1/f scl t high t su.st a t hd.st a t hd.da t t su.da t t su.st o t buf t dh t aa t low t r scl wp sda (in) sda (out) t su.wp t hd.wp write cycle timing scl sda d0 in w rite data ack (address (n)) t wc (internally controlled) stop condition start condition r10ds0122ej0100 rev.1.00 page 5 of 15 aug. 23, 2012
R1EV24002ASAS0I preliminary pin function serial clock (scl) the scl pin is used to control serial input/output data timing. the scl input is used to positive edge clock data into eeprom device and negative edge clock data out of each device. maximum clock rate is 400 khz. serial input/output data (sda) the sda pin is bidirectional for serial data transfer. the sda pin needs to be pulled up by resistor as that pin is open- drain driven structure. use proper resistor value for your system by considering v ol , i ol and the sda pin capacitance. except for a start condition and a stop condition which will be discussed later, the sda transition needs to be completed during the scl low period. data validity (sda data chang e timing waveform) scl sda data change data change note: high-to-low and low-to-high change of sda should be done during the scl low period. device address (a0, a1, a2) eight devices can be wired for one common data bus line as maximum. device address pins are used to distinguish each device and device address pins should be connected to v cc or v ss . when device address code provided from sda pin matches corresponding hard-wired device address pins a0 to a2, that one device can be activated. pin connections for a0 to a2 pin connection memory size max connect number a2 a1 a0 note 2k bit 8 v cc /v ss v cc /v ss v cc /v ss note: 1. during floating, ?v cc /v ss ? are fixed to v ss , because these are internally pulled-down. write protect (wp) when the write protect pin (wp) is high, the write protection feature is enabled and operates as shown in the following table. also, acknowledgment "0" is outputted after inputting device address and memory address. after inputting write data, acknowledgment "1" (no ack) is outputted. when the wp is low, write operation for all memory arrays are allowed. the read op eration is always activated irrespective of the wp pin status. the wp pin is internally pulled-down to vss. write ope rations for all memory array are allowed if unconnected. write protect area write protect area wp pin status 2k bit v ih full (2k bit) v il normal read/write operation r10ds0122ej0100 rev.1.00 page 6 of 15 aug. 23, 2012
R1EV24002ASAS0I preliminary functional description start condition a high-to-low transition of the sda with the scl high is needed in order to start read, write operation (see start condition and stop condition). stop condition a low-to -high transition of the sda with the scl high is a stop condition. the stand-by operation starts after a read sequence by a stop condition. in the case of write operation, a stop condition te rminates the write data inputs and place the device in a internally-timed write cycle to the memories. after the internally-timed write cycle which is specified as t wc , the device enters a standby mode (see write cycle timing). start condition and stop condition scl sda (in) stop condition start condition acknowledge all addresses and data words are serially transmitted to and from in 8-bit words. the receiver sends a zero to acknowledge that it has received each word. this happens during ninth clock cycl e. the transmitter keeps bus open to receive acknowledgment from the receiver at the ninth cloc k. in the write operation, eeprom sends a zero to acknowledge after receiving every 8-bit words. in th e read operation, eeprom se nds a zero to acknowledge after receiving the device address word. afte r sending read data, the eeprom waits acknowledgment by k eeping bus open. if the eeprom receives zero as an acknowledge, it sends r ead data of next address. if the eeprom receives acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a stand-by mode. if the eeprom receives neither acknowle dgment "0" nor a stop conditi on, the eeprom keeps bus open without sending read data. acknowledge timing waveform scl sda in sda out 12 8 9 acknowledge out r10ds0122ej0100 rev.1.00 page 7 of 15 aug. 23, 2012
R1EV24002ASAS0I preliminary r10ds0122ej0100 rev.1.00 page 8 of 15 aug. 23, 2012 device addressing the eeprom device requires an 8-bit device address word follo wing a start condition to enable the chip for a read or a write operation. the device address word consists of 4-bit device code, 3-bit device address code and 1-bit read/write(r/w) code. the most significant 4-bit of the de vice address word are used to distinguish device type and this eeprom uses ?1010? fixed code. the device address word is followed by the 3-bit device address code a2, a1, a0. the device address code selects one device out of eight devices which are connected to the bus. this means that the device is selected if the inputted 3-bit device address code is equal to the corresponding hard-wired a2 to a0 pins status. the eighth bit of the device address word is the read/w rite(r/w) bit. a write operation is initiated if this bit is ?0? and a read operation is initiated if this bit is ?1?. th e eeprom turns to a stand-by state if the device code is not ?1010? or device address code doesn?t coincide with status of the correspond hard-wired device address pins. device address word device address word (8-bit) device code (fixed) device address code r/w code * 1 2k 1 0 1 0 a2 a1 a0 r/w note: 1. r/w=?1? is read and r/w = ?0? is write.
R1EV24002ASAS0I preliminary write operations (wp =low ) byte write: (write operation during wp =low status ) a write operation requires an 8-bit device address word with r/w = ?0?. then the eeprom sends acknowledgment "0" at the ninth clock cycle. after these, the 2k bit eepr om receives 8-bit memory addre ss words. upon receipt of this memory address, the eeprom outputs acknowledgment "0" and receives a following 8-bit write data. after receipt of write data, the eeprom ou tputs acknowledgment "0". if the ee prom receives a stop condition, the eeprom enters an internally-timed write cycle and terminates receipt of sc l, sda inputs until completion of the write cycle. the eeprom returns to a standby mode after completion of the write cycle. byte write operation device address memory address write data (n) 2k 1010 w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop start ack ack r/w ack wp page write: the eeprom is capable of the page write operation which allo ws any number of bytes up to 8 bytes to be written in a single write cycle. the page write is the same sequence as the byte write except for inputting the more write data. the page write is initiated by a start condition, device address word, memory address(n) and write data (dn) with every ninth bit acknowledgment. the eeprom enters the page write operation if the eeprom receives more write data (dn+1) instead of receiving a stop cond ition. the a0 to a2 address bits are automatically incremen ted upon receiving write data (dn+1). the eeprom can continue to receive write da ta up to 8 bytes. if the a0 to a2 address bits reaches the last address of the page, the a0 to a2 address bits will roll over to the first address of the same page and previous write data will be overwritten. upon receiving a stop c ondition, the eeprom stops receiving write data and enters internally-timed write cycle. page write operation device address memory address write data (n+m) write data (n) 2k 1010 w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d5 d4 d3 d2 d1 d0 stop start ack ack ack ack r/w wp r10ds0122ej0100 rev.1.00 page 9 of 15 aug. 23, 2012
R1EV24002ASAS0I preliminary write operations (wp =high ) byte write: (write operation during wp =high status ) a write operation requires an 8-bit device address word with r/w = ?0?. then the eeprom sends acknowledgment "0" at the ninth clock cycle. after these, the 2k bit eepr om receives 8-bit memory addre ss. upon receipt of this memory address, the eeprom outputs ack nowledgment "0". after receipt of 8- bit write data, the eeprom outputs acknowledgment "1" (no ack) . then the eeprom write operations are not allowed. byte write operation device address memory address write data (n) 2k 1010 w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop start ack ack r/w no ack wp page write: the page write is the same sequence as the byte write. the page write is initiated by a start condition, device address word and memory address(n) with every ninth bit acknowledgment"0". but after inputting write data(dn) , the eeprom outputs acknowledgment "1" (no ack ). then the eeprom write operations are not allowed. page write operation device address memory address write data (n+m) write data (n) 2k 1010 w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d5 d4 d3 d2 d1 d0 stop start ack no ack ack r/w wp no ack r10ds0122ej0100 rev.1.00 page 10 of 15 aug. 23, 2012
R1EV24002ASAS0I preliminary acknowledge polling: acknowledge polling feature is used to show if the eeprom is in a internally-timed write cycle or not. this feature is initiated by the stop condition after inputting write data. this requires the 8-bit device address word following the start condition during a internally-timed write cycle. acknow ledge polling will operate when the r/w code = ?0?. acknowledgment ?1? (no acknowledgment) shows the eep rom is in a internally-timed write cycle and acknowledgment ?0? shows that the internally-timed write cycle has completed. see write cycle polling using ack. write cycle polling using ack send write command send stop condition to initiate write cycle send start condition send device address word with r/w = 0 send memory address send start condition send stop condition send stop condition proceed random addre ss read operation proceed write operati on next operation is addressing the memory y es y es no no ack returned r10ds0122ej0100 rev.1.00 page 11 of 15 aug. 23, 2012
R1EV24002ASAS0I preliminary read operation there are three read operations: current address read, ran dom read, and sequential read. read operations are initiated the same way as write operations with the exception of r/w = ?1?. current address read: the internal address counter maintains the last address accessed during the la st read or write operation, with incremented by one. current address read accesses the address kept by the internal address counter. after receiving a start condition and the device address word (r/w is ?1?), the eeprom outputs the 8-bit current address data from the most significant bit following acknowledgment ?0?. if the eeprom receives acknowledgment ?1? (no acknowledgment) and a following stop condition, the eeprom stops the read operation and is turned to a standby state. in case the eeprom has accessed the last address of the last page at previous read operation, the current address will roll over and returns to zero address. in case the eeprom ha s accessed the last address of the page at previous write operation, the current address will roll over within page addres sing and returns to the first address in the same page. the current address is valid while power is on. the current address after power on will be indefinite. the random read operation described below is necessary to define the memory address. current address read operation 2k device address read data (n+1) start stop 1010 r d7 d6 d5 d4 d3 d2 d1 d0 ack no ack r/w r10ds0122ej0100 rev.1.00 page 12 of 15 aug. 23, 2012
R1EV24002ASAS0I preliminary random read: this is a read operation with defined re ad address. a random read requires a dummy write to set read address. the eeprom receives a start condition, de vice address word (r/w=0) and memory address 8-bit sequentially. the eeprom outputs acknowledgment ?0? after receiving memory address then enters a current address read with receiving a start condition. the eeprom outputs the read data of the ad dress which was defined in the dummy write operation. after receiving acknowledg ment ?1?(no acknowledgment) and a following stop condition, the eeprom stops the random read operation and returns to a standby state. random read operation @@@ notes: 1. 2nd device address code (#) should be same as 1st (@). device address device address memory address read data (n) 2k 1010 ### 1010 r w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop start start ack no ack ack r/w ack r/w dummy write current address read sequential read: sequential reads are initiated by either a current addre ss read or a random read. if the eeprom receives acknowledgment ?0? after 8-bit r ead data, the read address is incremented and the next 8-bit read data are coming out. this operation can be continued as long as the eeprom receives acknowledgment ?0?. the address will roll over and returns address zero if it reaches the last address of the last page. the sequential read can be continued after roll over. the sequential read is terminated if the eeprom receives acknowledgment ?1 ? (no acknowledgment) and a following stop condition. sequential read operation device address read data (n+m) read data (n+1) read data (n+2) 2k 1010 r d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 stop start ack no ack ack r/w ack r10ds0122ej0100 rev.1.00 page 13 of 15 aug. 23, 2012
R1EV24002ASAS0I preliminary r10ds0122ej0100 rev.1.00 page 14 of 15 aug. 23, 2012 notes data protection at v cc on/off when v cc is turned on or off, noise on the scl and sda inputs generated by external circuits (cpu, etc) may act as a trigger and turn the eeprom to unintentional program mode . to prevent this unintentional programming, this eeprom has a power on reset function. be careful of the notices described below in order for the power on reset function to operate correctly. ? scl and sda should be fixed to v cc or v ss during v cc on/off. low to high or high to low transition during v cc on/off may cause the trigger for the unintentional programming. ? v cc should be turned off after the eeprom is placed in a standby state. ? v cc should be turned on from the ground level (v ss ) in order for the eeprom not to enter the unintentional programming mode. ? v cc turn on rate should be slower than 2 ? s/v. noise suppression time this eeprom have a noise suppression function at scl and sd a inputs, that cut noise of width less than 50 ns. be careful not to allow noise of width more than 50 ns. power source noise countermeasures in order to suppress power-source-noise which causes malfunction of the device, it is recommended to put 0.1uf bypass-capacitor (such as a monolithic ceramic capacitor wh ich has good high-frequency characteristics) between v cc and v ss , and shorten the wiring leng th between the capacitor and v cc /v ss terminals as much as possible. device address input, write protect input these ca n be used in the open state because these are pulled down inside the device. but pl ease note that the noise does not enter due to wiring connections at the floating state. if you connect the wiring, we recommend that you connect to vcc or vss to avoid malfunction due to noise.
R1EV24002ASAS0I preliminary package dimensions R1EV24002ASAS0I (prsp0008df-b / previous code: fp-8dbv) note) 1. dimensions"*1 (nom)"and"*2" do not incl ude mold flash. 2. dim ension"*3"does not include trim offset. 0.69 0.10 1.27 5.84 6.20 0.400.35 5.15 max nom min dimension in millimeters symbol reference 1.73 0.889 0.60 0.406 3.90 0.254 0.14 0.102 0.45 0.250.20 0.15 6.02 8 0 0.25 1.06 4.89 e h e l a d e a 2 a 1 b p b 1 c x y z l 1 c 1 previous code jeita package code renesas code prsp0008df-b fp-8dbv mass[typ.] 0.08g p-sop8-3.9x4.89-1.27 terminal cross section (ni/pd/au plating) l 1 a 1 c detail f l y s s 5 8 4 f *1 *2 *3 mx 1 index mark e z a e d b p b p h e r10ds0122ej0100 rev.1.00 page 15 of 15 aug. 23, 2012
all trademarks and registered trademarks are t he property of their respective owners. c - 1 revision history r1ev2400 2asas0i data sheet description rev. date page summary 1.00 aug. 23, 2012 initial issue
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